High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices by stacking chips vertically stacked have been introduced. Benefits of the 3D memory devices include a plurality of core chips stacked with an interface chip and the memory controller, which allow wide bandwidth buses with high transfer rates between functional blocks in the plurality of core chips and the interface chip, and a considerably smaller footprint. Thus, the 3D memory devices contribute to large memory capacity, higher memory access speed and chip size reduction. The 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).
As for inter-chip interconnections among stacked chips in a package, there are two types: wired interconnections; and wireless inter connections. As for wired interconnections, for example, microbumps for two chips or through silicon vias for two or more chips may be used. As for wireless interconnections, for example, capacitive coupling for two chips or inductive coupling for two or more chips may be employed. Recent proximity wireless communication technology exhibits about the same level of performance as wired link technology. For example, the proximity wireless communication technology may be comparable with the wired link technology in terms of data rates, reliability, power consumption, size, and connections.
To facilitate inductive coupling with coils, each chip of a plurality of chips stacked on a substrate or an interposer has coils, and data transmission between chips may be performed by inductive coupling. FIG. 1A is a schematic diagram of inductive coupling between two semiconductor chips in a semiconductor device. FIG. 1B is a cross-sectional schematic diagram of inductive coupling between the two semiconductor chips in the semiconductor device. For example, the semiconductor device 1 may include two semiconductor chips 2a and 2b. For example, the semiconductor chip 2a may be stacked on the semiconductor chip 2b. The semiconductor chip 2a may include a plurality of transmitter coils 3a and 3b attached at one face of (e.g., a bottom face) of the semiconductor chip 2a. The semiconductor chip 2b may include a plurality of receiver coils 3c and 3d attached at one face of (e.g., a bottom face) of the semiconductor chip 2b. 
FIG. 2A is a simplified schematic diagram of the plurality of coils 3a to 3d in FIGS. 1A and 1B. Each of the transmitter coils 3a and 3b may flow an electric current responsive to a signal to be transmitted. For example, as shown in FIG. 2A, the transmitter coil 3a may flow a current in a first direction (e.g., the counterclockwise direction) responsive to a signal having a logic low level (e.g., “0”, a falling edge). The transmitter coil 3b may flow a current in a second direction opposite to the first direction (e.g., the clockwise direction) responsive to a signal having a logic high level (e.g., “1”, a rising edge). Due to the currents of the transmitter coils 3a and 3b, electromotive forces may be induced at the receiver coils 3c and 3d. The receiver coils 3c and 3d may replicate signals having the same logic level (e.g., “0” and “1”, respectively) as the transmitter coils 3a and 3b due to the electromotive forces. FIG. 2B is a data combination table showing possible sets of combinations of two bit data for transmission in FIG. 2A. Bit1 and Bit2 may be either the logic low level (“0”) or the logic high level (“1”). Thus there may be four combinations of possible two bit data patterns which may be expressed.